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[Crack Hack] aes

Description: AES Core Modules In this document I describe components designated to encoding and decoding using AES. aes enc — parametrizable component which can encrypt input data, using 128, 192 and 256 bit key, • aes dec — parametrizable component which can decrypt input data, using 128, 192 and 256 bit key, • key expansion — parametrizable component which can produce key expansion, using 128, 192 and 256 bit key,
Platform: | Size: 10070 | Author: liangraul | Hits:

[OS program] kenel_crypto

Description: 内核加解密算法 加解密函数库及其使用说明，详见附件。 find_cipher_by_name中参数ciphername可取的值为下面的组合，对应不同的模式: (des,des_ede3,aes,blowfish,cast5,dfc,idea,mars,rc5,rc6,serpent,twofish)-ecb (des,des_ede3,aes,blowfish,cast5,dfc,idea,mars,rc5,rc6,serpent,twofish)-cbc (des,des_ede3,aes,blowfish,cast5,dfc,idea,mars,rc6,serpent,twofish)-cfb struct cipher_implementation* ci中对应的可调用的method：encrypt_iv decrypt_iv encrypt decrypt 比如以des-cbc为find_cipher_by_name的参数得到的ci调用encrypt_iv，decrypt_iv. find_digest_by_name中参数digestname可取的值: sha1 md5 struct digest_implementation* di中对应的可调用的method:open update digest close hmac 计算digest时调用di->digest，计算hmac时调用di->hmac. 注意：加载我们需要的cipher-*.o和digest-*.o之前需先加载cryptoapi.o。 -core encryption and decryption algorithm encryption and decryption functions and their use, as detailed in the annex. Find_cipher_by_name cipher desirable parameter values to the following portfolio, dealing with different modes : (des, des_ede3, Aes, blowfish, cast5, DFC, the idea, mars, RC5, production, serpent, twofish)- ecb ( des, des_ede3, Aes, blowfish, cast5, DFC, the idea, mars, RC5, production, serpent, twofish)- cbc (des, des_ede3, Aes, blowfish, cast5, DFC, the idea, mars, production, the serpent , twofish)- Sample struct cipher_implementation ci* corresponding the available method : encrypt_iv decrypt_iv encrypt decrypt such as a des-cbc find_cipher_by_name parameters for the ci call encrypt_iv, decrypt_iv. find_digest_by_name digestname desirable parameter values : sha1 md
Platform: | Size: 139264 | Author: xf | Hits:

[Crack Hack] aes_core

Description: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Platform: | Size: 79872 | Author: | Hits:

[Other] CipherOne6.0

Description: 本软件代码所有权属于Scaton Software Co.，你可以任意使用该代码，但不得以商业形式整体或整模块使用本代码。 scaton, 2006.2.16 CipherOne 加密钻石锁软件代码模块介绍： Zlib---zip压缩静态库代码，GNU代码 Rsaref---Rsa密钥处理及各算法代码库，RSA Lab拥有版权，Scaton Software增加了AES和IDEA算法代码 RsaKern---本软件加密、解密处理核心模块，Scaton Software拥有版权 CipShext---资源管理器扩展模块（右键菜单支持），Scaton Software拥有版权 CipherOne---加密、解密主界面程序，Scaton Software拥有版权 BCGCBPro---界面增强库，BCGSoft拥有版权 TLCtrl---树型组合列表控件代码，Tiger X原创，Scaton Software整理、排错，并添加排序功能等。 -ownership of the software code is Scaton Software Co.. , you can use the arbitrary code, but not on a commercial basis in whole or in the use of the entire module code. Scaton, 2006.2.16 CipherOne Diamond encryption locks on software code modules : Zlib--- zip code static libraries, GNU code Rsaref--- Rsa key processing algorithm and the code base, RSA Lab copyright owner. Scaton Software increased AES algorithm and IDEA-- the code RsaKern software encryption, decryption processing core module, Software copyright owner Scaton CipShext--- Resource Manager extension (right keys menu support), Scaton Software copyright owner CipherOne--- encryption, the main interface decryption procedures, Software copyright owner Scaton BCGCBPro--- enhanced interface library copyright TLCtrl BCGSoft-
Platform: | Size: 2314240 | Author: | Hits:

[Crack Hack] aes

Description: AES Core Modules In this document I describe components designated to encoding and decoding using AES. aes enc — parametrizable component which can encrypt input data, using 128, 192 and 256 bit key, • aes dec — parametrizable component which can decrypt input data, using 128, 192 and 256 bit key, • key expansion — parametrizable component which can produce key expansion, using 128, 192 and 256 bit key,-AES Core Modules In this document I describe components designated to encoding and decodingusing AES.aes enc- parametrizable component which can encrypt input data, using128, 192 and 256 bit key,
Platform: | Size: 10240 | Author: liangraul | Hits:

[Crack Hack] aes_core

Description: Verilog实现AES加密算法 密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied
Platform: | Size: 79872 | Author: yuansuchun | Hits:

[DSP program] aes

Description: 基于DM642的AES加密算法 很核心的～-DM642-based AES encryption algorithm is the core ~
Platform: | Size: 128000 | Author: nga | Hits:

[Crack Hack] aes_crypto_core_latest.tar

Description: Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
Platform: | Size: 961536 | Author: Arun | Hits:

[Crack Hack] AES

Description: AES算法的verilog代码，即AES算法IP核-ip core for AES
Platform: | Size: 13312 | Author: JJ | Hits:

[Other] aes_inv_cipher_top

Description: aes ip core, 128 bits
Platform: | Size: 12288 | Author: lai | Hits:

[Other systems] AES-Administration-and-Maintenance-Guide-Release-

Description: Implementing a telephony-enabled application using Avaya Telephony Services Application Programming Interface (TSAPI) requires an understanding of TSAPI core concepts of Session and Event Management, control services, and private data. This tutorial provides an overview of the TSAPI essentials, using code samples to demonstrate how to write a telephony-enabled application for the Avaya Communication Manager environment using the interfaces provided by the Avaya TSAPI implementation. INTENDED AUDIENCE This tutorial is intended for programmers who have a working knowledge of C/C++ programming on Windows platform and wish to implement telephony-enabled applications in an Avaya Aura™ Communication Manager environment. This tutorial is not meant to be an exhaustive introduction to TSAPI refer to Reference [1] for a complete understanding of the Avaya TSAPI implementation-Implementing a telephony-enabled application using Avaya Telephony Services Application Programming Interface (TSAPI) requires an understanding of TSAPI core concepts of Session and Event Management, control services, and private data. This tutorial provides an overview of the TSAPI essentials, using code samples to demonstrate how to write a telephony-enabled application for the Avaya Communication Manager environment using the interfaces provided by the Avaya TSAPI implementation. INTENDED AUDIENCE This tutorial is intended for programmers who have a working knowledge of C/C++ programming on Windows platform and wish to implement telephony-enabled applications in an Avaya Aura™ Communication Manager environment. This tutorial is not meant to be an exhaustive introduction to TSAPI refer to Reference [1] for a complete understanding of the Avaya TSAPI implementation
Platform: | Size: 591872 | Author: machrider24 | Hits:

[VHDL-FPGA-Verilog] aes_core.tar

Description: 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
Platform: | Size: 133120 | Author: weipingzhang | Hits:

[VHDL-FPGA-Verilog] aes-core

Description: Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
Platform: | Size: 88064 | Author: fujiwei | Hits:

[VHDL-FPGA-Verilog] AES-sopc--ip

Description: 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
Platform: | Size: 473088 | Author: rjt | Hits:

[VHDL-FPGA-Verilog] base-on-FPGA-AES-addkey-design

Description: 介绍了用FPGA实现AES算法所用的开发工具，开发语言和所选用的芯片，及AES算法的硬件实现方式。着重阐述了AES算法FPGA实现的总体设计框图，并副有部分源代码- introduce design tool,language and core of AES which base on FPGA,and AES hardware design.
Platform: | Size: 2184192 | Author: 邱绿 | Hits:

[Other] AES-IP-core-key-expansion-module

Description: AES IP核密钥扩展模块设计与仿真（设计过程及程序，测试程序）-AES IP core key expansion module design and simulation (the design process and procedures, test procedures)
Platform: | Size: 39936 | Author: 周涛 | Hits:

[Crack Hack] aes

Description: AES的IP核,AES的加密解密算法，包括密钥扩展程序-aes core verilog
Platform: | Size: 32768 | Author: 余金锁 | Hits:

[source in ebook] aes-core-include-testbentch

Description: aes core的verilog代码，包含测试代码和波形文件-aes core verilog code including testbentch
Platform: | Size: 105472 | Author: exirrl | Hits:

[Other] A-compact-AES-core-with-on-line-error-detection-f

Description: This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead.
Platform: | Size: 940032 | Author: ANU MOHAN | Hits:

[Crack Hack] AES-File-EnDecryptor-Writed-by-CSharp-master

Description: 使用 C# 编写的AEC文件加密核心代码源码。(Use C# to write the AEC file encryption core code source code.)
Platform: | Size: 54272 | Author: 地摊夫妻 | Hits:
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